A conventional sense amplifier generally addresses about 256 to 1,024 memory cells via a line, a so-called bitline. The conventional sense amplifier is more specifically a differential amplifier operating with a bitline and a complementary bitline which is used as a reference line.
A conventional technique for increasing the performances of dynamic DRAM memory consists in reducing the number of cells addressed by a sense amplifier (reference is also made to a reduction in the length of the bitline). However, a larger number of sense amplifiers has to be provided in order to address the whole of the cells making up the memory, which is expressed by a loss of global efficiency insofar that management of the memory consumes useful surface area to the detriment of the actual memory.
In order to react to this loss of efficiency, the article “A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier”, J Barth et al., ISSCC (2007), Pages: 486-487 shows an architectural hierarchy based on sense amplifiers, so-called micro-sense amplifiers, addressing via a local bitline, few cells (32 typically) but consisting of very few (typically three) transistors.
This article proposes an architecture in which the different memory cells are made on a silicon-on-insulator substrate (SOI). The different micro-sense amplifiers are, as for them, formed either on a bulk substrate or a SOI substrate.
Each micro-sense amplifier has two input terminals connected to two main bitlines RBL (Read Bitline) and WBL (Write Bitline) which will control the read/write operations of the cells addressed in parallel via the local bitline LBL connected to the output terminal of the micro-sense amplifier.
Resorting to two main bitlines proves to be a problem in that the architecture proposed by this article cannot be transposed for producing standalone memories and thus remains limited to the production of embedded memories.
Further, each micro-sense amplifier can only address a reduced number of memory cells (16 to 32 typically) so that a relatively large number of micro-sense amplifiers (from 64 k to 128 k for a 2 Mbit memory) has to be resorted to. In spite of the relatively reduced size of the micro-amplifier (only 3 transistors), the drawback mentioned earlier of significant surface consumption for the sense amplification function, to the detriment of the memory function, therefore partly remains.